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MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--May 30, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced that Texas Instruments has selected Synopsys' Scirocco(TM) VHDL simulator as a key component of the verification suite for their high performance digital signal processor (DSP) designs.

``Scirocco is used on our leading-edge designs, and is a part of our standard RTL regression tools within TI DSP,'' said Mike Fazeli worldwide EDA manager for DSP Based Designs at Texas Instruments (TI). ``Scirocco combines superior performance and ease of use, which has improved the verification of our designs and helped us realize our demanding time-to-market goals.''

Over the past year, TI has been using Scirocco as part of their verification environment, to verify their latest generation DSP designs. Scirocco combines the flexibility of event simulation with the speed and capacity of cycle-based algorithms to deliver the fastest VHDL simulation on the market. Scirocco's industry leading performance has allowed TI verification engineers to run more regression tests on their simulation server farm and gain significantly improved productivity.

``With the increasing size and complexity of ICs, our customers have been aggressively adopting VCS for Verilog simulation farms to dramatically improve simulation throughput,'' said Manoj Gandhi, general manager and sr. vice president of the Verification Technology Group at Synopsys. ``We are excited to see a similar trend with Scirocco and are thrilled that Texas Instruments is able to take advantage of Scirocco's performance for their VHDL RTL regression farm.''

Complete Functional Verification Solution

Synopsys provides a complete line of functional verification solutions supporting Verilog, VHDL, mixed-HDL, and mixed-signal for complex SoC designs aimed at achieving the highest functional coverage in the shortest amount of time. These solutions include Synopsys' VCS(TM) Verilog simulator, Scirocco(TM) VHDL simulator, VCS/Scirocco-MX mixed-HDL simulation, VERA(TM) testbench automation tool, CoverMeter(TM) Verilog code coverage analysis tool, DesignWare® verification IP, LEDA® programmable HDL checker, NanoSim(TM) circuit simulation, and Formality® equivalence checker.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronics systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys, Formality, DesignWare and VERA are registered trademarks of Synopsys, Inc. VCS, Scirocco, CoverMeter, and NanoSim are all trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Synopsys, Inc., Mountain View
     Renae Cunningham, 650/584-1902
     renae@synopsys.com
        or
     KVO Public Relations
     Amy Garland, 503/221-2387
     amy@kvo.com